Japanese

Academic Year	2026Year	School/Graduate School	Graduate School of Advanced Science and Engineering (Master's Course) Division of Advanced Science and Engineering Quantum Matter Program
Lecture Code	WSP06300	Subject Classification	Specialized Education
Subject Name	集積回路物理設計
Subject Name （Katakana）	シュウセキカイロブツリセッケイ
Subject Name in English	VLSI Physical Design
Instructor	NISHIZAWA SHINICHI
Instructor (Katakana)	ニシザワ　シンイチ
Campus	Higashi-Hiroshima	Semester/Term	1st-Year,  First Semester,  1Term
Days, Periods, and Classrooms	(1T) Mon7-8,Tues3-4：AdSM 405N
Lesson Style	Lecture	Lesson Style (More Details)	Face-to-face
Credits	2.0	Class Hours/Week	4	Language of Instruction	B : Japanese／English
Course Level	5 : Graduate Basic
Course Area（Area）	25 : Science and Technology
Course Area（Discipline）	11 : Electrical, Systems, and Control Engineering
Eligible Students
Keywords	Hardware description language, Verilog HDL, RISC-V
Special Subject for Teacher Education		Special Subject
Class Status within Educational Program (Applicable only to targeted subjects for undergraduate students)	Use Verilog HDL (Hardware Description Language) to understand digital circuit and its design.
Criterion referenced Evaluation (Applicable only to targeted subjects for undergraduate students)
Class Objectives /Class Outline	This lecture focuses on Verilog HDL and learns how to use Verilog HDL to design digital circuits and its verification via test bench. This lecture focuses on combinational circuit design, sequential circuit design and state machine to design simple digital circuits. Finally, this lecture focuses on simple RISC-V microprocessor core and learn its description and behavior.
Class Schedule	Lecture 1: Guidance, Introduction to Hardware Description Languages Lecture 2: Design and Simulation of Simple Circuits Lecture 3: Basic Grammar Lecture 4: Combinational Circuits 1: Basic Gates, Selectors, and Decoders Lecture 5: Combinational Circuits 2: Encoders and Arithmetic Circuits Lecture 6: Sequential Circuits 1: Latches and Flip-Flops Lecture 7: Sequential Circuits 2: Sequential Circuit Design Lecture 8: Sequential Circuits 3: State Machines Lecture 9: Simulation 1: Simulation Model Lecture 10: Simulation 2: Simulation Description Lecture 11: Microprocessor Design 1: Overview of RISC-V Architecture Lecture 12: Microprocessor Design 2: Instruction Decoder Design Lecture 13: Microprocessor Design 3: Arithmetic Logic Function Unit Design Lecture 14: Microprocessor Design 4: Assembly Programming Lecture 15: Summary Lecture 16: Final Exam
Text/Reference Books,etc.	Textbook: 小林 優，改訂 入門 Verilog HDL 記述，CQ出版社 (Japanese) Reference:  David Harris  and Sarah Harris, "Digital Design and Computer Architecture [RISC-V edition]," Morgan Kaufmann
PC or AV used in Class,etc.	Text, Handouts, Microsoft Teams
	(More Details)	Will offer handouts and recorded video
Learning techniques to be incorporated
Suggestions on Preparation and Review	Install Verilog HDL simulator to simulate the behavior of digital circuit designed by Verilog HDL.
Requirements	Prease not delay the submission of report.
Grading Method	Report (30 points) and final exam (70 points). More than 60 points is the mandatory.
Practical Experience
Summary of Practical Experience and Class Contents based on it
Message
Other
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