K6406020 Computer architecture

Hiroshima University Syllabus

Japanese

Academic Year 2026Year School/Graduate School School of Engineering

Lecture Code K6406020 Subject Classification Specialized Education

Subject Name コンピューターアーキテクチャ

Subject Name
（Katakana）コンピューターアーキテクチャ

Subject Name in
English Computer architecture

Instructor NISHIZAWA SHINICHI

Instructor
(Katakana) ニシザワ　シンイチ

Campus Higashi-Hiroshima Semester/Term 2nd-Year, Second Semester, 3Term

Days, Periods, and Classrooms (3T) Weds1-4：ENG 104

Lesson Style Lecture Lesson Style
(More Details) Face-to-face

Credits 2.0 Class Hours/Week 4 Language of Instruction J : Japanese

Course Level 3 : Undergraduate High-Intermediate

Course Area（Area） 25 : Science and Technology

Course Area（Discipline） 12 : Electronics

Eligible Students

Keywords Computer architecture, logic circuits, sequential circuits, RISC-V, assembly language, microarchitecture

Special Subject for Teacher Education 　 Special Subject 　

Class Status
within Educational
Program
(Applicable only to targeted subjects for undergraduate students) Learn the basics of computer architecture, which is the foundation of computer systems, and how to design it.
Criterion referenced
Evaluation
(Applicable only to targeted subjects for undergraduate students) Program of Semiconductor Systems
（Abilities and Skills）
・Concepts, knowledge and methods which are the basis for studies related to semiconductor engineering.
・Ability to apply basic concepts, knowledge, and methods of semiconductor engineering to concrete/technical problems.

Class Objectives
/Class Outline This course covers the fundamentals of computer architecture, which is the backbone of computer systems, and covers design methods for basic logic functions, combinational circuits, sequential circuits, and small-scale building blocks. It also covers computer architecture and microarchitecture, which is the detailed internal implementation of computer architecture.

Class Schedule Lecture 1: Guidance, From Zero to One
Lesson 2: Combinational Logic Circuits
Lesson 3: Sequential Circuits
Lesson 4: Finite State Machines
Lesson 5: Digital Building Blocks
Lesson 6: Memory Arrays
Lesson 7: Midterm Exam. Computer Architecture 1: RISC-V and Assembly Language
Lesson 8: Computer Architecture 2: Assembly Language Programming
Lesson 9: Microarchitecture 1: Single-Cycle Processors and Their Performance
Lesson 10: Microarchitecture 2: Multi-Cycle Processors
Lesson 11: Microarchitecture 3: Pipeline Processors
Lesson 12: Memory Systems 1: Overview
Lesson 13: Memory Systems 2: Cache
Lesson 14: Memory Systems 3: Virtual Memory
Lesson 15: Summary
Lesson 16: Final Exam

Text/Reference
Books,etc. Textbook: Sarah Harris, David Harris, Digital Design and Computer Architecture, RISC-V Edition, Morgan Kaufmann Publishers (Both Japanese and English are available)
Reference: Kenji Yoshise, A Complete Introduction to Computer Architecture with RISC-V, Gijutsu Hyoronsha. (Japanese)
Reference: Videos and PDF materials will be available.

PC or AV used in
Class,etc. Handouts, Microsoft Teams, moodle

(More Details) Videos and PDF materials will be available.

Learning techniques to be incorporated

Suggestions on
Preparation and
Review Please utilize recorded video for review.

Requirements

Grading Method The grade will be determined based on a comprehensive assessment of the midterm and final exams. A score of 60% or higher on the midterm exam (40%) and final exam (60%) is required to receive credits.

Practical Experience

Summary of Practical Experience and Class Contents based on it

Message

Other This course is connected from the "Programming Exercise I," "Logic System Design," and "CMOS Logic Circuit Design (Logic Circuit Design II)" lectures. Please fully understand the content of these subjects before taking this course.
Taking the "Programming Exercise II" lecture will make it easier to understand this course.
This course connects to the "Hardware Description Language" lecture.

Please fill in the class improvement questionnaire which is carried out on all classes.
Instructors will reflect on your feedback and utilize the information for improving their teaching.

Academic Year	2026Year	School/Graduate School	School of Engineering
Lecture Code	K6406020	Subject Classification	Specialized Education
Subject Name	コンピューターアーキテクチャ
Subject Name （Katakana）	コンピューターアーキテクチャ
Subject Name in English	Computer architecture
Instructor	NISHIZAWA SHINICHI
Instructor (Katakana)	ニシザワ　シンイチ
Campus	Higashi-Hiroshima	Semester/Term	2nd-Year, Second Semester, 3Term
Days, Periods, and Classrooms	(3T) Weds1-4：ENG 104
Lesson Style	Lecture	Lesson Style (More Details)	Face-to-face

Credits	2.0	Class Hours/Week	4	Language of Instruction	J : Japanese
Course Level	3 : Undergraduate High-Intermediate
Course Area（Area）	25 : Science and Technology
Course Area（Discipline）	12 : Electronics
Eligible Students
Keywords	Computer architecture, logic circuits, sequential circuits, RISC-V, assembly language, microarchitecture
Special Subject for Teacher Education		Special Subject
Class Status within Educational Program (Applicable only to targeted subjects for undergraduate students)	Learn the basics of computer architecture, which is the foundation of computer systems, and how to design it.
Criterion referenced Evaluation (Applicable only to targeted subjects for undergraduate students)	Program of Semiconductor Systems （Abilities and Skills）・Concepts, knowledge and methods which are the basis for studies related to semiconductor engineering. ・Ability to apply basic concepts, knowledge, and methods of semiconductor engineering to concrete/technical problems.
Class Objectives /Class Outline	This course covers the fundamentals of computer architecture, which is the backbone of computer systems, and covers design methods for basic logic functions, combinational circuits, sequential circuits, and small-scale building blocks. It also covers computer architecture and microarchitecture, which is the detailed internal implementation of computer architecture.
Class Schedule	Lecture 1: Guidance, From Zero to One Lesson 2: Combinational Logic Circuits Lesson 3: Sequential Circuits Lesson 4: Finite State Machines Lesson 5: Digital Building Blocks Lesson 6: Memory Arrays Lesson 7: Midterm Exam. Computer Architecture 1: RISC-V and Assembly Language Lesson 8: Computer Architecture 2: Assembly Language Programming Lesson 9: Microarchitecture 1: Single-Cycle Processors and Their Performance Lesson 10: Microarchitecture 2: Multi-Cycle Processors Lesson 11: Microarchitecture 3: Pipeline Processors Lesson 12: Memory Systems 1: Overview Lesson 13: Memory Systems 2: Cache Lesson 14: Memory Systems 3: Virtual Memory Lesson 15: Summary Lesson 16: Final Exam
Text/Reference Books,etc.	Textbook: Sarah Harris, David Harris, Digital Design and Computer Architecture, RISC-V Edition, Morgan Kaufmann Publishers (Both Japanese and English are available) Reference: Kenji Yoshise, A Complete Introduction to Computer Architecture with RISC-V, Gijutsu Hyoronsha. (Japanese) Reference: Videos and PDF materials will be available.
PC or AV used in Class,etc.	Handouts, Microsoft Teams, moodle
(More Details)	Videos and PDF materials will be available.
Learning techniques to be incorporated
Suggestions on Preparation and Review	Please utilize recorded video for review.
Requirements
Grading Method	The grade will be determined based on a comprehensive assessment of the midterm and final exams. A score of 60% or higher on the midterm exam (40%) and final exam (60%) is required to receive credits.
Practical Experience
Summary of Practical Experience and Class Contents based on it
Message
Other	This course is connected from the "Programming Exercise I," "Logic System Design," and "CMOS Logic Circuit Design (Logic Circuit Design II)" lectures. Please fully understand the content of these subjects before taking this course. Taking the "Programming Exercise II" lecture will make it easier to understand this course. This course connects to the "Hardware Description Language" lecture.
Please fill in the class improvement questionnaire which is carried out on all classes. Instructors will reflect on your feedback and utilize the information for improving their teaching.

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