K6407020 Hardware description language

Hiroshima University Syllabus

Japanese

Academic Year 2026Year School/Graduate School School of Engineering

Lecture Code K6407020 Subject Classification Specialized Education

Subject Name ハードウェア記述言語

Subject Name
（Katakana）ハードウェアキジュツゲンゴ

Subject Name in
English Hardware description language

Instructor NISHIZAWA SHINICHI

Instructor
(Katakana) ニシザワ　シンイチ

Campus 　 Semester/Term 2nd-Year, Second Semester, 4Term

Days, Periods, and Classrooms (4T) Fri1-4：ENG 111

Lesson Style Lecture Lesson Style
(More Details) Face-to-face

Credits 2.0 Class Hours/Week 4 Language of Instruction J : Japanese

Course Level 3 : Undergraduate High-Intermediate

Course Area（Area） 25 : Science and Technology

Course Area（Discipline） 12 : Electronics

Eligible Students

Keywords Hardware Description Language，Verilog HDL，RISC-V

Special Subject for Teacher Education 　 Special Subject 　

Class Status
within Educational
Program
(Applicable only to targeted subjects for undergraduate students) Use Verilog HDL as a hardware description language, learn how to describe digital circuits and their test bench.
Criterion referenced
Evaluation
(Applicable only to targeted subjects for undergraduate students) Program of Semiconductor Systems
（Abilities and Skills）
・Concepts, knowledge and methods which are the basis for studies related to semiconductor engineering.
・Ability to apply basic concepts, knowledge, and methods of semiconductor engineering to concrete/technical problems.

Class Objectives
/Class Outline This course focuses on Verilog HDL, a hardware description language widely used in digital circuit design, and provides an understanding of its description method and verification methods through simulation. It also covers the description of combinational circuits, sequential circuits, and state machines, and finally describes and understands the core circuit of a simple microprocessor.

Class Schedule Lecture 1: Guidance, Introduction to Hardware Description Languages
Lecture 2: Design and Simulation of Simple Circuits
Lecture 3: Basic Grammar
Lecture 4: Combinational Circuits 1: Basic Gates, Selectors, and Decoders
Lecture 5: Combinational Circuits 2: Encoders and Arithmetic Circuits
Lecture 6: Sequential Circuits 1: Latches and Flip-Flops
Lecture 7: Sequential Circuits 2: Sequential Circuit Design
Lecture 8: Sequential Circuits 3: State Machines
Lecture 9: Simulation 1: Simulation Model
Lecture 10: Simulation 2: Simulation Description
Lecture 11: Microprocessor Design 1: Overview of RISC-V Architecture
Lecture 12: Microprocessor Design 2: Instruction Decoder Design
Lecture 13: Microprocessor Design 3: Arithmetic Logic Function Unit Design
Lecture 14: Microprocessor Design 4: Assembly Programming
Lecture 15: Summary
Lecture 16: Final Exam

Text/Reference
Books,etc. Textbook: Yu Kobayashi, Revised Introduction to Verilog HDL Description, CQ Publishing (Japanese)
Reference: Sarah Harris, David Harris, Digital Design and Computer Architecture, RISC-V Edition, Morgan Kaufmann Publishers
Reference: Videos and PDF materials will be available.

PC or AV used in
Class,etc. Handouts, Microsoft Teams, moodle

(More Details) Videos and PDF materials will be available.

Learning techniques to be incorporated

Suggestions on
Preparation and
Review Install the specified Verilog HDL simulation environment on a Windows laptop and deepen your understanding by writing and simulating Verilog HDL.

Requirements

Grading Method The report and final exam will be combined. A total score of 60 points or more for the report (30 points) and final exam (70 points) is required to receive credits.

Practical Experience

Summary of Practical Experience and Class Contents based on it

Message

Other This course connects with the "Programming Exercises I," "Logic System Design," "CMOS Logic Circuit Design (Logic Circuit Design II)," and "Computer Architecture" lectures. Please fully understand the content of these subjects before taking this course.
Taking the "Programming Exercises II" lecture will make it easier to understand this course.

Please fill in the class improvement questionnaire which is carried out on all classes.
Instructors will reflect on your feedback and utilize the information for improving their teaching.

Academic Year	2026Year	School/Graduate School	School of Engineering
Lecture Code	K6407020	Subject Classification	Specialized Education
Subject Name	ハードウェア記述言語
Subject Name （Katakana）	ハードウェアキジュツゲンゴ
Subject Name in English	Hardware description language
Instructor	NISHIZAWA SHINICHI
Instructor (Katakana)	ニシザワ　シンイチ
Campus		Semester/Term	2nd-Year, Second Semester, 4Term
Days, Periods, and Classrooms	(4T) Fri1-4：ENG 111
Lesson Style	Lecture	Lesson Style (More Details)	Face-to-face

Credits	2.0	Class Hours/Week	4	Language of Instruction	J : Japanese
Course Level	3 : Undergraduate High-Intermediate
Course Area（Area）	25 : Science and Technology
Course Area（Discipline）	12 : Electronics
Eligible Students
Keywords	Hardware Description Language，Verilog HDL，RISC-V
Special Subject for Teacher Education		Special Subject
Class Status within Educational Program (Applicable only to targeted subjects for undergraduate students)	Use Verilog HDL as a hardware description language, learn how to describe digital circuits and their test bench.
Criterion referenced Evaluation (Applicable only to targeted subjects for undergraduate students)	Program of Semiconductor Systems （Abilities and Skills）・Concepts, knowledge and methods which are the basis for studies related to semiconductor engineering. ・Ability to apply basic concepts, knowledge, and methods of semiconductor engineering to concrete/technical problems.
Class Objectives /Class Outline	This course focuses on Verilog HDL, a hardware description language widely used in digital circuit design, and provides an understanding of its description method and verification methods through simulation. It also covers the description of combinational circuits, sequential circuits, and state machines, and finally describes and understands the core circuit of a simple microprocessor.
Class Schedule	Lecture 1: Guidance, Introduction to Hardware Description Languages Lecture 2: Design and Simulation of Simple Circuits Lecture 3: Basic Grammar Lecture 4: Combinational Circuits 1: Basic Gates, Selectors, and Decoders Lecture 5: Combinational Circuits 2: Encoders and Arithmetic Circuits Lecture 6: Sequential Circuits 1: Latches and Flip-Flops Lecture 7: Sequential Circuits 2: Sequential Circuit Design Lecture 8: Sequential Circuits 3: State Machines Lecture 9: Simulation 1: Simulation Model Lecture 10: Simulation 2: Simulation Description Lecture 11: Microprocessor Design 1: Overview of RISC-V Architecture Lecture 12: Microprocessor Design 2: Instruction Decoder Design Lecture 13: Microprocessor Design 3: Arithmetic Logic Function Unit Design Lecture 14: Microprocessor Design 4: Assembly Programming Lecture 15: Summary Lecture 16: Final Exam
Text/Reference Books,etc.	Textbook: Yu Kobayashi, Revised Introduction to Verilog HDL Description, CQ Publishing (Japanese) Reference: Sarah Harris, David Harris, Digital Design and Computer Architecture, RISC-V Edition, Morgan Kaufmann Publishers Reference: Videos and PDF materials will be available.
PC or AV used in Class,etc.	Handouts, Microsoft Teams, moodle
(More Details)	Videos and PDF materials will be available.
Learning techniques to be incorporated
Suggestions on Preparation and Review	Install the specified Verilog HDL simulation environment on a Windows laptop and deepen your understanding by writing and simulating Verilog HDL.
Requirements
Grading Method	The report and final exam will be combined. A total score of 60 points or more for the report (30 points) and final exam (70 points) is required to receive credits.
Practical Experience
Summary of Practical Experience and Class Contents based on it
Message
Other	This course connects with the "Programming Exercises I," "Logic System Design," "CMOS Logic Circuit Design (Logic Circuit Design II)," and "Computer Architecture" lectures. Please fully understand the content of these subjects before taking this course. Taking the "Programming Exercises II" lecture will make it easier to understand this course.
Please fill in the class improvement questionnaire which is carried out on all classes. Instructors will reflect on your feedback and utilize the information for improving their teaching.

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