WSP06100 VLSI Layout Design

Hiroshima University Syllabus

Japanese

Academic Year 2025Year School/Graduate School Graduate School of Advanced Science and Engineering (Master's Course) Division of Advanced Science and Engineering Quantum Matter Program

Lecture Code WSP06100 Subject Classification Specialized Education

Subject Name VLSIレイアウト設計

Subject Name
（Katakana）ブイエルエスアイレイアウトセッケイ

Subject Name in
English VLSI Layout Design

Instructor TAKAHASHI ATSUSHI,See the "Class Schedule" of the syllabus

Instructor
(Katakana) タカハシ　アツシ,シラバスジュギョウケイカクトウサンショウ

Campus Across Campuses (videoconferencing, etc.) Semester/Term 1st-Year, Second Semester, 4Term

Days, Periods, and Classrooms (4T) Tues3-4,Fri3-4

Lesson Style Lecture Lesson Style
(More Details) Online (simultaneous interactive)

Credits 2.0 Class Hours/Week 4 Language of Instruction E : English

Course Level 6 : Graduate Advanced

Course Area（Area） 25 : Science and Technology

Course Area（Discipline） 12 : Electronics

Eligible Students

Keywords Layout, Partition, Placement, Routing

Special Subject for Teacher Education 　 Special Subject 　

Class Status
within Educational
Program
(Applicable only to targeted subjects for undergraduate students)
Criterion referenced
Evaluation
(Applicable only to targeted subjects for undergraduate students)

Class Objectives
/Class Outline VLSIs that support information and communications engineering are realized through system and behavior design, logic and circuit design, layout design, and performance verification. Among these design stages, layout design is often called physical design or place and route by the procedures included in it. The purpose of this lecture is to understand the fact that layout design is one of the most important design stages by which the performance of VLSI is highly affected, and to acquire basic layout design methods.

Class Schedule Class 1 Layout design in VLSI design Explain the overview of layout design
Class 2 Layout design process Explain the overview of layout design process
Class 3 Time complexity of algorithm Explain the overview of time complexity of algorithm
Class 4 Partitioning (1) overview Explain the overview of partitioning
Class 5 Partitioning (2) logic partitioning Explain the overview of methods for logic partitioning
Class 6 Placement (1) overview Explain the overview of placement
Class 7 Placement (2) representation Explain the overview of representations for placement Explain the overview of placement
Class 8 Placement (3) search method Explain the overview of search methods for placement
Class 9 Routing (1) overview Explain the overview of routing algorithm
Class 10 Routing (2) planar routing Explain the overview of methods for planar routing
Class 11 Routing (3) design for manufacturing Explain the overview of methods for design for manufacturing
Class 12 Routing (4) length minimization Explain the overview of methods for length minimization
Class 13 Routing (5) channel routing Explain the overview of methods for channel routing
Class 14 Routing (6) clock routing Explain the overview of methods for clock routing

Text/Reference
Books,etc. Textbook(s)：None
Reference books, course materials, etc.：
Handouts will be distributed at the beginning of class when necessary

PC or AV used in
Class,etc.

(More Details)

Learning techniques to be incorporated

Suggestions on
Preparation and
Review To enhance effective learning, students are encouraged to spend approximately 100 minutes preparing for class and another 100 minutes reviewing class content afterwards (including assignments) for each class.
They should do so by referring to textbooks and other course material.

Requirements This course is part of the Integrated Green-niX College program (a joint program with Institute of Science Tokyo, Toyohashi University of Technology, Nagaoka University of Technology and Meiji University, based on a memorandum of understanding for credit transfer related to semiconductor talent development). Please note that you cannot register for this course unless you have completed the special audit student application procedure at your respective university beforehand.

Grading Method Studnets' level of understanding on the basic layout design methods will be assessed. Learning achievement is evaluated by the quality of the written reports.

Practical Experience

Summary of Practical Experience and Class Contents based on it

Message

Other

Please fill in the class improvement questionnaire which is carried out on all classes.
Instructors will reflect on your feedback and utilize the information for improving their teaching.

Academic Year	2025Year	School/Graduate School	Graduate School of Advanced Science and Engineering (Master's Course) Division of Advanced Science and Engineering Quantum Matter Program
Lecture Code	WSP06100	Subject Classification	Specialized Education
Subject Name	VLSIレイアウト設計
Subject Name （Katakana）	ブイエルエスアイレイアウトセッケイ
Subject Name in English	VLSI Layout Design
Instructor	TAKAHASHI ATSUSHI,See the "Class Schedule" of the syllabus
Instructor (Katakana)	タカハシ　アツシ,シラバスジュギョウケイカクトウサンショウ
Campus	Across Campuses (videoconferencing, etc.)	Semester/Term	1st-Year, Second Semester, 4Term
Days, Periods, and Classrooms	(4T) Tues3-4,Fri3-4
Lesson Style	Lecture	Lesson Style (More Details)	Online (simultaneous interactive)

Credits	2.0	Class Hours/Week	4	Language of Instruction	E : English
Course Level	6 : Graduate Advanced
Course Area（Area）	25 : Science and Technology
Course Area（Discipline）	12 : Electronics
Eligible Students
Keywords	Layout, Partition, Placement, Routing
Special Subject for Teacher Education		Special Subject
Class Status within Educational Program (Applicable only to targeted subjects for undergraduate students)
Criterion referenced Evaluation (Applicable only to targeted subjects for undergraduate students)
Class Objectives /Class Outline	VLSIs that support information and communications engineering are realized through system and behavior design, logic and circuit design, layout design, and performance verification. Among these design stages, layout design is often called physical design or place and route by the procedures included in it. The purpose of this lecture is to understand the fact that layout design is one of the most important design stages by which the performance of VLSI is highly affected, and to acquire basic layout design methods.
Class Schedule	Class 1 Layout design in VLSI design Explain the overview of layout design Class 2 Layout design process Explain the overview of layout design process Class 3 Time complexity of algorithm Explain the overview of time complexity of algorithm Class 4 Partitioning (1) overview Explain the overview of partitioning Class 5 Partitioning (2) logic partitioning Explain the overview of methods for logic partitioning Class 6 Placement (1) overview Explain the overview of placement Class 7 Placement (2) representation Explain the overview of representations for placement Explain the overview of placement Class 8 Placement (3) search method Explain the overview of search methods for placement Class 9 Routing (1) overview Explain the overview of routing algorithm Class 10 Routing (2) planar routing Explain the overview of methods for planar routing Class 11 Routing (3) design for manufacturing Explain the overview of methods for design for manufacturing Class 12 Routing (4) length minimization Explain the overview of methods for length minimization Class 13 Routing (5) channel routing Explain the overview of methods for channel routing Class 14 Routing (6) clock routing Explain the overview of methods for clock routing
Text/Reference Books,etc.	Textbook(s)：None Reference books, course materials, etc.： Handouts will be distributed at the beginning of class when necessary
PC or AV used in Class,etc.
(More Details)
Learning techniques to be incorporated
Suggestions on Preparation and Review	To enhance effective learning, students are encouraged to spend approximately 100 minutes preparing for class and another 100 minutes reviewing class content afterwards (including assignments) for each class. They should do so by referring to textbooks and other course material.
Requirements	This course is part of the Integrated Green-niX College program (a joint program with Institute of Science Tokyo, Toyohashi University of Technology, Nagaoka University of Technology and Meiji University, based on a memorandum of understanding for credit transfer related to semiconductor talent development). Please note that you cannot register for this course unless you have completed the special audit student application procedure at your respective university beforehand.
Grading Method	Studnets' level of understanding on the basic layout design methods will be assessed. Learning achievement is evaluated by the quality of the written reports.
Practical Experience
Summary of Practical Experience and Class Contents based on it
Message
Other
Please fill in the class improvement questionnaire which is carried out on all classes. Instructors will reflect on your feedback and utilize the information for improving their teaching.

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